The Lincoln Graph Processor enables the efficient computation of interactive graph analytics on large-scale graph databases.
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The Lincoln Graph Processor technology enables the computation of interactive graph analytics on large-scale graph databases that cannot be analyzed efficiently even on today's high-performance server-class and supercomputing systems.

Lincoln Graph Processor Technology Overview

Lincoln Graph Processor hardware architecture has been designed to minimize power consumption while increasing edge search performance, leveraging

  • a specialized inter-processor data communications network that can maintain performance as the number of processors increases, and
  • an accelerator-based processing chip optimized for local memory search and power efficiency.

At the heart of the architecture is a novel communication network that can accommodate up to a million processors. The multidimensional network topology, routing, and physical link protocols have been designed from the ground up to allow graph edge information to efficiently flow and traverse the system.

The processing board for the new graph processor is shown.
The processing board for the new graph processor is shown.

The key differences in comparison to traditional network technology include

  • high cross-section bandwidth, which defines the rate of information exchange between all of the processors;
  • low congestion-routing protocols, which leverage randomization and small packet sizes to achieve unprecedented network efficiency;
  • a low-diameter topology, which allows the addition of processing resources without a loss of performance.

All these features are critical for executing graph analysis and finding information that is distributed across the entire system.

A prototype of the latest Lincoln Graph Processor system hardware was developed to demonstrate the benefits of the architecture. This prototype used field-programmable gate array (FPGA) technology; however, to push performance even further, the same architectural concepts can be ported to an application-specific integrated circuit (ASIC), which would provide another order of magnitude of performance and power efficiency. This revolutionary level of performance would provide an unparalleled level of insight and analysis to enable new research and scientific discovery.

Benefits

  • Novel communication network that can accommodate up to a million processors, providing 100 to 1,000 times traditional graph-edge search performance
  • Accelerator-based processing chip optimized for local memory search and power efficiency
  • Specialized hardware architecture that supports data mapping and load balancing

Potential Use Cases

  • Large-scale cyber forensics
  • Product recommendation and consumer pattern analysis
  • Financial fraud detection

Additional Resources

U.S. Patents 8,819,272; 8,751,556; and 8,190,943

More Information

W. S. Song et al., "Novel Graph Processor Architecture," MIT Lincoln Laboratory Journal, vol. 20, no. 1, pp. 92–104, 2013.