Time-Interleaved Multi-modulus Frequency Divider

Frequency dividers and event counters are common in digital electronics and communication systems, typically used in generating a signal with a frequency that is a multiple of an input frequency. However, conventional frequency divider circuits can consume a significant amount of power, especially when operating at high frequencies, and can pose a challenge to power efficiency. Further exacerbating this issue, current solutions such as analog-based frequency dividers, while effective at signal generation and modulation, are not suitable for all applications. Also, traditional techniques have problems delivering precision at high frequencies. Thus, there is a need for a more power-efficient solution that maintains accurate performance at high frequencies.

Technology Description

The technology is a multi-modulus frequency divider and event counter that leverages time-interleaved signals obtained from a received clock signal. Each of these signals is then directed to a bit counter, and the output from each bit counter is routed to a multiplexer. A dedicated multiplexer selection unit dictates over time which output signal from the bit counters is shown at the multiplexer's output. What sets this technology apart is the transition frequency of the bits in the time-interleaved clock signals permitting various circuit components, like the bit counters, to be implemented as CMOS components. Compared to traditional frequency divider circuits operating at high clock frequencies, this frequency divider provides a more energy-efficient solution. This efficient power usage is the crucial differentiator for this technology.