Publications

As the demand for higher data rates increases, commercial analog-to-digital converters (ADCs) are more commonly being implemented with multiple on-chip converters whose outputs are time-interleaved. The distortion generated by time-interleaved ADCs is now not only a function of the nonlinear behavior of the constituent circuitry, but also mismatches associated with...

Systems currently being developed to operate across wide bandwidths with high sensitivity requirements are limited by the inherent dynamic range of a receiver's analog and mixed-signal components. To increase a receiver's overall linearity, we have developed a digital NonLinear EQualization (NLEQ) processor which is capable of extending a receiver's dynamic...

In this paper, we present an architecture and semiblind identification method for a polyphase nonlinear equalizer (pNLEQ). Such an equalizer is useful for extending the dynamic range of time-interleaved analog-to-digital converters (ADCs). Our proposed architecture is a polyphase extension to other architectures that partition the Volterra kernel into small nonlinear...

In this paper, we present the cube coefficient subspace (CCS) architecture for linearizing power amplifiers (PAs), which divides the overparametrized Volterra kernel into small, computationally efficient subkernels spanning only the portions of the full multidimensional coefficient space with the greatest impact on linearization. Using measured results from a Q-Band solid...

The performance of linear programming techniques that are applied in the signal identification and reconstruction process in compressed sensing (CS) is governed by both the number of measurements taken and the number of nonzero coefficients in the discrete basis used to represent the signal. To enhance the capabilities of CS...

Digital baseband predistortion (DBP) is not particularly well suited to linearizing wideband power amplifiers (PAs); this is due to the exorbitant price paid in computational complexity. One of the underlying reasons for the computational complexity of DBP is the inherent inefficiency of using a sufficiently deep memory and a high...

This paper describes the need for High Performance Computing (HPC) to facilitate the development and implementation of a nonlinear equalizer that is capable of mitigating and/or eliminating nonlinear distortion to extend the dynamic range of radar front-end receivers decades beyond the analog state-of-the-art. The search space for the optimal nonlinear...