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A wafer-scale 3-D circuit integration technology

October 1, 2006
  |
Journal Article
Author:
James A. Burns
…
Published in:
IEEE Trans. Electron Devices, Vol. 53, No. 10, October 2006, pp. 2507-2516.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

The rationale and development of a wafer-scale three-dimensional (3-D) integrated circuit technology are described. The essential elements of the 3-D technology are integrated circuit fabrication on silicon-on-insulator wafers, precision wafer-wafer alignment using an in-house-developed alignment system, low-temperature wafer-wafer bonding to transfer and stack active circuit layers, and interconnection of the circuit layers with dense-vertical connections with sub-[Omega] 3-D via resistances. The 3-D integration process is described as well as the properties of the four enabling technologies. The wafer-scale 3-D technology imposes constraints on the placement of the first lithographic level in a wafer-stepper process. Control of wafer distortion and wafer bow is required to achieve submicrometer vertical vias. Three-tier digital and analog 3-D circuits were designed and fabricated. The performance characteristics of a 3-D ring oscillator, a 1024 x 1024 visible imager with an 8-um pixel pitch, and a 64 x 64 Geiger-mode laser radar chip are described.
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Summary

The rationale and development of a wafer-scale three-dimensional (3-D) integrated circuit technology are described. The essential elements of the 3-D technology are integrated circuit fabrication on silicon-on-insulator wafers, precision wafer-wafer alignment using an in-house-developed alignment system, low-temperature wafer-wafer bonding to transfer and stack active circuit layers, and interconnection of the...

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A wafer-scale 3-D circuit integration technology

Laser radar imager based on 3D integration of Geiger-mode avalanche photodiodes with two SOI timing circuit layers

February 6, 2006
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Conference Paper
Author:
Brian F. Aull
…
Published in:
ISSCC 2006, IEEE Int. Solid-State Circuits Conf., 6-9 February 2006.
Topic:
ladar
R&D area:
R&D group:

Summary

We have developed focal-plane arrays and laser-radar (ladar) imaging systems based on Geiger-mode avalanche photodiodes (APDs) integrated with high-speed all-digital CMOS timing circuits. A Geiger-mode APD produces a digital pulse upon detection of a single photon. This pulse is used to stop a fast digital counter in the pixel circuit, thereby measuring photon arrival time. This "photon-to-digital conversion" yields quantum-limited sensitivity and noiseless readout, enabling high-performance ladar systems. Previously reported focal planes, based on bump bonding or epoxy bonding the APDs to foundry chips, had coarse (100um) pixel spacing and 0.5ns timing quantization.
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Summary

We have developed focal-plane arrays and laser-radar (ladar) imaging systems based on Geiger-mode avalanche photodiodes (APDs) integrated with high-speed all-digital CMOS timing circuits. A Geiger-mode APD produces a digital pulse upon detection of a single photon. This pulse is used to stop a fast digital counter in the pixel circuit...

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Laser radar imager based on 3D integration of Geiger-mode avalanche photodiodes with two SOI timing circuit layers

Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology

June 19, 2005
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Conference Paper
Author:
Vyshnavi Suntharalingam
…
Published in:
2005 IEEE Int. Solid-Stat Circuits Conf. Digest of Technical Papers, Pt.1, 19-25 June 2005, p. 356-357.
Topic:
integrated circuit
R&D area:
R&D group:

Summary

In this paper a 3D integrated 1024x1024, 8um pixel visible image sensor fabricated with oxide-to-oxide wafer bonding and 2-um square 3-D-vias in every pixel is presented. The 150mm wafer technology integrates a low-leakage, deep-depletion, 100% fill factor photodiode layer to a 3.3-V, 0.35-um gate length fully depleted (FD) SOI CMOS readout circuit layer.
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Summary

In this paper a 3D integrated 1024x1024, 8um pixel visible image sensor fabricated with oxide-to-oxide wafer bonding and 2-um square 3-D-vias in every pixel is presented. The 150mm wafer technology integrates a low-leakage, deep-depletion, 100% fill factor photodiode layer to a 3.3-V, 0.35-um gate length fully depleted (FD) SOI CMOS...

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Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology

Monolithic 3.3V CCD/SOI-CMOS Imager Technology

December 10, 2000
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Conference Paper
Author:
Vyshnavi Suntharalingam
…
Published in:
IEEE Int. Eelctron Devices Mtg., 10-13 December 2000, pp. 30.3.1-30.3.4.
Topic:
semiconductor (CMOS)
R&D area:
R&D group:

Summary

We have developed a merged CCD/SOI-CMOS technology that enables the fabrication of monolithic, low-power imaging systems on a chip. The CCD's, fabricated in the bulk handle wafer, have charge-transfer inefficiencies of about 1x10(-5) and well capacities of more than 100,000 electrons with 3.3-V clocks and 8x8um pixels. Fully depleted 0.35pm SOI-CMOS ring oscillators have stage delay of 48ps at 3.3V. We demonstrate for the first time an integrated image sensor with charge-domain A/D conversion and on-chip clocking.
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Summary

We have developed a merged CCD/SOI-CMOS technology that enables the fabrication of monolithic, low-power imaging systems on a chip. The CCD's, fabricated in the bulk handle wafer, have charge-transfer inefficiencies of about 1x10(-5) and well capacities of more than 100,000 electrons with 3.3-V clocks and 8x8um pixels. Fully depleted 0.35pm...

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Monolithic 3.3V CCD/SOI-CMOS Imager Technology

SOI wafer selection for CCD/SOI-CMOS technology [Abstract]

October 2, 2000
  |
Conference Paper
Author:
Vyshnavi Suntharalingam
…
Published in:
2000 IEEE Int. SOI Conf. Proc., 2-5 October 2000, pp. 136-137.
Topic:
semiconductor (CMOS)
R&D area:
R&D group:

Summary

We have developed a process that monolithically integrates fully depleted SOI CMOS (FDSOI) with high-performance CCD image sensors. This integrated technology that enables charged-coupled devices (CCD's) to be in close proximity to, yet isolated from, FDSOI circuits. This approach exploits both the advantages of FDSOI (fast, low-power CMOS with potentially enhanced radiation performance) and those of CCD's (high quantum efftciency, low noise, and architectural flexibility). This 3.3 V, 0.3 mu m CCD/FDSOI-CMOS technology thus enables fabrication of low-power, compact imaging systems. Material requirements for CCD imagers are perhaps the most stringent of any device and require special attention to the quality of the bulk or handle wafer. We report here characterization of various SOI handle wafers for use in fabrication of bulk imaging devices.
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Summary

We have developed a process that monolithically integrates fully depleted SOI CMOS (FDSOI) with high-performance CCD image sensors. This integrated technology that enables charged-coupled devices (CCD's) to be in close proximity to, yet isolated from, FDSOI circuits. This approach exploits both the advantages of FDSOI (fast, low-power CMOS with potentially...

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SOI wafer selection for CCD/SOI-CMOS technology [Abstract]
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