Publications

Graphene transistors are made by transferring a thin graphene film grown on Ni onto an insulating SiO2 substrate. The properties and integration of these graphene-on-insulator transistors are presented and compared to the characteristics of devices made from graphitized SiC and exfoliated graphene flakes.

At Lincoln Laboratory, we have established a three dimensional (3D) integrated circuit (IC) technology that has been developed and demonstrated over eight designs, bonding two or three active circuit layers or tiers to form monolithically integrated 3D circuits. This technology has been used to successfully demonstrate a large-area 8 x...

This paper describes the behavior of top-gated transistors fabricated using carbon, specifically epitaxial graphene on SiC, as the active material. Although graphene devices have been built before, in this paper, we provide the first demonstration and systematic evaluation of arrays of a large number of transistors produced using standard microelectronics...

Introduction At Lincoln Laboratory, we have established a three dimensional (3D) integrated circuit (IC) technology that has been developed and demonstrated over seven designs, bonding two or three active circuit layers or tiers to form monolithically integrated 3D circuits. Key features of our 3DIC technology include fully depleted SOI (FDSOI)...

The rationale and development of a wafer-scale three-dimensional (3-D) integrated circuit technology are described. The essential elements of the 3-D technology are integrated circuit fabrication on silicon-on-insulator wafers, precision wafer-wafer alignment using an in-house-developed alignment system, low-temperature wafer-wafer bonding to transfer and stack active circuit layers, and interconnection of the...

We have developed focal-plane arrays and laser-radar (ladar) imaging systems based on Geiger-mode avalanche photodiodes (APDs) integrated with high-speed all-digital CMOS timing circuits. A Geiger-mode APD produces a digital pulse upon detection of a single photon. This pulse is used to stop a fast digital counter in the pixel circuit...

In this paper a 3D integrated 1024x1024, 8um pixel visible image sensor fabricated with oxide-to-oxide wafer bonding and 2-um square 3-D-vias in every pixel is presented. The 150mm wafer technology integrates a low-leakage, deep-depletion, 100% fill factor photodiode layer to a 3.3-V, 0.35-um gate length fully depleted (FD) SOI CMOS...

The performance is reported for a new microelectromechanical structure (MEMS) cantilever microswitch. We report on both dc- and capacitively-contacted microswitches. The dc-contacted microswitches have contact resistance of less than 1 ohm, and the RF loss of the switch up to 40 GHz in the closed position is 0.1-0.2 dB. Capacitively-contacted...

We have developed a merged CCD/SOI-CMOS technology that enables the fabrication of monolithic, low-power imaging systems on a chip. The CCD's, fabricated in the bulk handle wafer, have charge-transfer inefficiencies of about 1x10(-5) and well capacities of more than 100,000 electrons with 3.3-V clocks and 8x8um pixels. Fully depleted 0.35pm...

We have developed a process that monolithically integrates fully depleted SOI CMOS (FDSOI) with high-performance CCD image sensors. This integrated technology that enables charged-coupled devices (CCD's) to be in close proximity to, yet isolated from, FDSOI circuits. This approach exploits both the advantages of FDSOI (fast, low-power CMOS with potentially...